Appeal from the United States Patent and Trademark Office, Patent Trial and Appeal Board in Reexamination Nos. 95/000,166 and 95/001,122.
JAMES R. BARNEY, Finnegan, Henderson, Farabow, Garrett & Dunner, LLP, of Washington, DC, argued for appellant. With him on the brief were J. MICHAEL JAKES, MOLLY R. SILFEN, and AIDAN C. SKOYLES. Of counsel was KATHLEEN DALEY.
Before RADER,[*] MOORE and REYNA, Circuit Judges.
Reyna, Circuit Judge
This is an appeal from an inter partes reexamination of claims 26 and 28 of U.S. Patent No. 6,426,916 (" the '916 patent" ). The Patent Trial and Appeal Board (" Board" ) at the United States Patent and Trademark Office (" PTO" ) found that the claims were anticipated by U.S. Patent No. 4,734,909 to Bennett (" Bennett" ). Patent owner Rambus, Inc. (" Rambus" ) appeals the Board's anticipation decision, arguing that Bennett does not disclose the claimed " value that is representative of an amount of time to transpire after which the memory device outputs the first amount of data."
After oral argument, requestor Micron Technology, Inc. (" Micron" ) moved to withdraw from this case, which we granted in a separate order. Rambus has the right to appeal the Board's rejection of its claims irrespective of Micron's participation in this appeal. See 35 U.S.C. § 315(a)(1) (2006). Thus, despite Micron's withdrawal, a live controversy regarding the patentability of Rambus's claims remains before us for resolution. We do not reach Micron's alternate grounds for affirming the Board, because these arguments have been withdrawn. As discussed below, we reverse the Board's anticipation decision as unsupported by substantial evidence.
The '916 patent discloses a method and system for improving the efficiency of computer memory. Broadly speaking, a computer may need to transfer data between different memory devices, such as between a memory controller (sometimes called a master) and a memory device that stores data (sometimes called a slave). This data may be transferred via a " bus," such as a series of wires, or " lines," that connect the memory device and the controller. Some memory systems include a wait signal that is sent, sometimes over a wait line, from a memory device to a memory controller that says the memory device is not ready to receive or send data. The wait signal may also indicate when the memory device will be ready to send data.
Relevant to this appeal, signals may be transferred via a bus using either " dedicated" lines or " multiplexed" lines. If a signal has a dedicated line on the bus it means that this signal does not share its line with other signals. This can be analogized to a multiple lane road where each car (signal) has its own lane, which it can travel on at any time without interfering with a car on another lane. By contrast,
two signals may be multiplexed on a single line. For example, if a " wait" signal and a " data" signal are time-division multiplexed, they share a single line on the bus in a time based manner and cannot use the line at the same time. This may be analogized to a one lane road that cars cannot drive on at the same time.
If two memory devices want to use the bus at the same time but, for technical reasons not relevant here, they cannot, the process by which the computer chooses which device goes first is called " arbitration." A memory device may be ready to send data to a memory controller but, if it " loses" arbitration, it will have to wait ...